Jitter may occur on the output of non-return-to-zero (NRZ) data transmitter at high frequency data-rate, e.g., at or above 5 Gbps. It is preferable to minimize the jitter to reduce its negative impact on the timing margin of the receiver at the other end and the overall link quality.
Many factors contribute to the jitter, for example the source and external factors including but not limited to crosstalk, impedance mismatch, connector non idealities. As the external factors are less controllable, it is desirable to lower the jitter contribution from the source as much as possible. The jitter in the transmitter clock generator signal may be propagated by further jitter generation and jitter transfer, especially when the data is transmitted from a clock data recovery (CDR) or another source with significant noise.
In many conventional systems, it is necessary to have a transmitter clock generator that is configured to filter out the source high frequency jitter and generate a transmit clock signal having a low noise. This is in general accomplished by using a low noise phase locked loop (also referred to as “PLL”) with a low bandwidth and a low noise oscillator. The best performances are achieved by using LC oscillators. However, if multiple independent lanes with different data rates must coexist on a same chip, for example as shown in FIG. 1, the necessity of including multiple LC oscillators on a single chip would cause new problems, such as, frequency beating due to noise coupling between inductors. Moreover, higher power and bigger area are required for implementing systems using multiple LC oscillators, compared to the ones using ring oscillators, in order to achieve a satisfactory jitter performance. Therefore, many multiple-lanes designs nevertheless use ring oscillators despite their worst performance in term of noise generation and power trade-off.